1. Field of the Invention
The present invention relates to relates to a method for collecting failure information for memories tested using an embedded memory test controller.
2. Description of Related Art
Adams et al U.S. Pat. No. 5,912,901 granted on Jun. 15, 1999 for xe2x80x9cMethod and Built-in Self-test Apparatus for Testing an Integrated Circuit which Capture Failure Information for a Selected Failurexe2x80x9d discloses a built-in self-test (BIST) apparatus and method for testing an integrated circuit which enables capture of failure data for a selected failure. The BIST apparatus comprises a clock generator, which generates at least a first clock signal, and a built-in self-tester, which applies predetermined input data patterns to the integrated circuit in response to the first clock signal. The BIST apparatus further includes a data comparator for comparing output data received from the integrated circuit with expected output data. The data comparator detects a failure within the integrated circuit when the output data received from the integrated circuit differs from the expected output data. The BIST apparatus also includes a clock controller that disables the first clock signal in response to the detection of a selected occurrence of a failure. By enabling testing of the integrated circuit to be halted upon the occurrence of a selected failure, failure analysis of the integrated circuit is enhanced.
Adams et al. suggest that the method can be used to capture all failure data of a memory by iteratively applying the method. However, collecting all information in this manner can be extremely time consuming and would collect failure information about repetitive failures that would not add any new information. By way of example, FIG. 2 illustrates a memory 10 which contains 64 words of two-bits each for a total of 128 bits. These bits are organized in arrays or banks 12 and 14. Each array has a number of rows and columns. Each bit of an array is accessed by applying a row address and a column address. In the example, three bits are used to access one of the eight rows and two bits are used to access one of the four groups of columns. Each bank is shown as arranged into two groups 16 and 18, each group having two groups of two columns (because words have two bits each). The bank address bit is used to select the bank to be accessed. Actual memories usually have many more rows and columns. The symbol xe2x80x98Xxe2x80x99 in FIG. 2 indicates bits that appear to be defective after applying a test. In the first bank, Bank 0, all bits of column xe2x80x9810xe2x80x99 of group 18 of Bank 0 are marked as defective. In the second bank, Bank 1, all bits of the fifth row (row xe2x80x98100xe2x80x99) are marked as defective. However, the actual cause of these defects reside in the circuitry used to access the bits. For example, a defective bit line could be responsible for the first set of failures. A defective word line could be responsible for the second set of failures. It will be seen that collecting specific information about each of the individual errors which appear to be defective in this situation would not provide useful information. In real memories, it would be extremely time consuming to capture detailed information about all such failures just to conclude that the access to the entire column or row is defective. Thus, a different method is needed to minimize the amount of detailed information that needs to be captured without sacrificing the ability to identify the root causes of the failures.
Another limitation of the Adams et al method is that it assumes that all failures are repeatable, i.e., that if the same test is applied to a memory, the same failures will occur at the same bit locations. Unfortunately, this is often not the case especially when testing the memory at high speed. Even at reduced speed, some defects will cause failures to be intermittent. The Adams et al method will miss some of the failures in such situations.
The present invention seeks to provide a method of testing memories which provide failure information about a complete column, row, bank, etc., as well as detailed information about each individual failure. The method thus reduces considerably the amount of time required to collect failure information, but the information is much more useful in terms of determining the root cause of some errors.
One aspect of the present invention is generally defined as a method for collecting failure information when testing a memory, comprising: performing a test of the memory according to a test algorithm, and, while performing the test, counting failure events which occur after a predetermined number of masked events; stopping the test upon occurrence of a stopping criterion which comprises one of occurrence of a first failure event, a change of a test operation; a change of a memory column address; a change of a memory row address; a change of a memory bank address; and a change of a test algorithm phase; and storing failure information.
Another aspect of the present invention is generally defined as an improvement in a memory test controller for use in an integrated circuit for testing memory, the improvement comprising an event counter for counting predetermined events and responsive to a stopping criterion signal by generating a freeze signal, the event counter being responsive to an active failure signal for counting failure events; and control logic for controlling memory test operations, the control logic being operable for generating the stopping criterion signal and being responsive to the freeze signal for stopping the test controller test.